15.5 Event-Based Spatially Zooming Neural Interface IC with 10nW/Input Reconfigurable-Inverter Fabric and Input-Adaptive Quantization

Large-scale neural interface ICs have tens of thousands of electrodes [1]–[3], enabling a wide range of applications including neural prostheses and therapeutic neuromodulation. However, the human brain contains 86 billion neurons and new frontiers in brain interfacing, such as understanding memory and cognition, will benefit from concurrent access to a million or more of implanted electrodes [4]. Modern microfabrication technologies, including silicon wafer thinning [1], allow for dense co-integration of electrodes and transistors on the same flexible substrate [1,4-6] and overcome the issue of the mega-scale electrode interconnect bottleneck [7]. The key remaining challenges are the low energy efficiency of neural ADCs and the high output data rate [4]. For example, one million inputs require 10nW/input ADC power - for a tissue-safe 10mW ADC total power budget [8], and a 200Gb/s wireless link - for 8b conversion at 25kHz [4]. However, the power dissipation of neural ADCs, either dedicated [9]–[12] or time-multiplexed [1-3,13], is over 50× higher, and implantable radios are at least 100× slower [14]–[15]. To address these challenges, neural spiking sparsity has been exploited in both off-line [16]–[17] and on-line [8], [18] methods of optimum electrode selection, but this leads to significant losses in recorded information [17] and requires <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{near}-\cup \mathrm{W}/\text{inp}\lfloor\vert \mathrm{t}$</tex> power due to static circuit biasing [8], [18], respectively.