4.6 A 0.8V, 31ppm/°C, −40dB DC-to-GHz Power-Supply-Rejection Standard-Vth Core-MOS-Only Voltage Reference with a 294µm<sup>2</sup>Area
PVT-independent voltage references (VRs) are critical analog blocks for data converters and sensors in system-on-chips <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{SoCs})$</tex>. As advanced technology nodes continue to scale down, the demand for core-device-only reference circuits that can operate at core-domain supply voltages <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\text{DD}}\mathrm{S})$</tex> is becoming increasingly important for area-shrinkage and reliability considerations. Working at sub-1V <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{DD}}$</tex> is a significant design barrier for BJT-based VRs due to the headroom limitation of the emitter-base junction voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\text{EB}})$</tex> of BJTs and the drain-source saturation voltage of the current sources. Reference [1] presents a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0 7\mathrm{V}$</tex> BJT-based VR using deep-n-well (DNW) base-structure PNP devices with lower <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{EB}}$</tex> requirements, but DNWs usually are not compatible with a standard logic CMOS process. Charge-pump [2] and switched-capacitor [3] techniques can reduce the supply of BJT-based reference circuits to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0 5\mathrm{V}$</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0 85\mathrm{V}$</tex>. However, switching-mode VRs typically require large filters to remove output ripples, which results in an extra area penalty.
Authors
- Szu-Lin Liu
- Kenny Hsieh
- Yichen Lu (ORCID: https://orcid.org/0000-0002-9436-0079)
- Wei-Lin Lai
- Yung-Chow Peng
- Bei-Shing Lien
Institutions
- Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
Publication Details
- Published
- 2025-02-16
- DOI
- https://doi.org/10.1109/isscc49661.2025.10904560
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00