36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating

Demand for chiplet integration using 2.5D or 3D packaging has surged due to the AI/MLdriven growth in computing performance. Universal Chiplet Interconnect Express (UCIe) has been developed to standardize chiplet interconnects, focusing on bandwidth density, energy efficiency, and latency. Dynamic clock gating is crucial for reducing power consumption, but transitioning from clock-gated to ungated modes introduces challenges due to the instantaneous current surge (Di/Dt), which can cause significant supply voltage droop. This droop leads to data sampling misalignment and bit errors. This paper presents a 32Gb/s, 64-lane UCIe module with a matched-delay architecture designed to address these challenges and ensure low power and low latency operation.

Authors

Institutions

Publication Details

Published
2025-02-16
DOI
https://doi.org/10.1109/isscc49661.2025.10904767
Citations
8
Primary Topic
Semiconductor Lasers and Optical Devices
Type
article
Field-Weighted Citation Impact
5.84
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating

Kenny Hsieh, Alan J. Drake, Chao-Chieh Li, Shenggao Li et al.
8 citations
Semiconductor Lasers and Optical Devices
5.84
article

36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating

Kenny Hsieh, Alan J. Drake, Chao-Chieh Li, Shenggao Li, Wen-Hung Huang, Wei‐Chih Chen, Jimmy Wang, Hsin‐Hung Kuo, Mu-Shan Lin, Hua-qiang Liao, A. Yin, Meng-Hsuan Wu, Kevin Lin, Thomas Basso, Nai‐Chen Cheng, Yu‐Chi Chen, Chien-Chun Tsai, D.P. King, Jianxun Huang, Chin-Hua Wen, Yu‐Jie Huang, Shu-Chun Yang, Huanhuan Ke, Paul Ranucci, Farsheed Mahmoudi, Nicholas Amatruda, William Polanco, Anwar Kashem
article en
8 citations

Abstract

Demand for chiplet integration using 2.5D or 3D packaging has surged due to the AI/MLdriven growth in computing performance. Universal Chiplet Interconnect Express (UCIe) has been developed to standardize chiplet interconnects, focusing on bandwidth density, energy efficiency, and latency. Dynamic clock gating is crucial for reducing power consumption, but transitioning from clock-gated to ungated modes introduces challenges due to the instantaneous current surge (Di/Dt), which can cause significant supply voltage droop. This droop leads to data sampling misalignment and bit errors. This paper presents a 32Gb/s, 64-lane UCIe module with a matched-delay architecture designed to address these challenges and ensure low power and low latency operation.

Taiwan Semiconductor Manufacturing Company (United States) (US), Taiwan Semiconductor Manufacturing Company (China) (CN), Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
Affordable and clean energy
Openalex Percentile: Top 4%
Semiconductor Lasers and Optical Devices
5.84
DOISourceOpenAlex
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.