24.4 A 10b 3GS/s Time-Domain ADC with Mutually Exclusive Metastability Correction and Wide Common-Mode Input

Metastable trajectories in comparators pose unpredictable and non-Gaussian error behaviors in the A/D conversion, which cannot be tolerated by applications such as low-bit-error-rate serial link receivers, radar, and instrumentation [1]–[5]. Time-domain (TD) AOCs [6]–[11] have demonstrated a superior speed to their voltage-domain (VD) SAR and pipeline counterparts thanks to the technology scaling. However, the metastability artifact of the TD ADC is often overlooked, which can be severe under a stringent time deadline and is worth great attention. In literature, TD circuits are often leveraged to facilitate the “metastability detector” [1], while the metastability events indeed cannot be detected because the detector itself can experience metastability. They often detect the error within the loop time, which therefore involves limited additional gain and decision time with extra load on the critical path, leading to a potentially diminished return on error probability <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{P}_{\mathrm{m}\mathrm{e}\mathrm{t}\mathrm{a}})$</tex>. Prior work [2], [3] decouples such constraints by pipelining the comparator decisions with additional latches, thus allowing extra gain and time on the detection. This proper unresolved-decision (UD) detection demonstrates an outstanding <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{P}_{\mathrm{m}\mathrm{e}\mathrm{t}\mathrm{a}}$</tex> in a time-interleaved SAR architecture [3]. However, it compromises latency with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{P}_{\mathrm{m}\mathrm{e}\mathrm{t}\mathrm{a}}$</tex>, which is feasible in SARs but not in multistep ADCs.

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Published
2025-02-16
DOI
https://doi.org/10.1109/isscc49661.2025.10904818
Citations
1
Primary Topic
Analog and Mixed-Signal Circuit Design
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article
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article

24.4 A 10b 3GS/s Time-Domain ADC with Mutually Exclusive Metastability Correction and Wide Common-Mode Input

Chi–Hang Chan, Wei Zhang, Yan Zhu, Z Liu et al.
1 citations
Analog and Mixed-Signal Circuit Design
0.67
article

24.4 A 10b 3GS/s Time-Domain ADC with Mutually Exclusive Metastability Correction and Wide Common-Mode Input

Chi–Hang Chan, Wei Zhang, Yan Zhu, Z Liu, Minglei Zhang, Rui P. Martins
article en
1 citations

Abstract

Metastable trajectories in comparators pose unpredictable and non-Gaussian error behaviors in the A/D conversion, which cannot be tolerated by applications such as low-bit-error-rate serial link receivers, radar, and instrumentation [1]–[5]. Time-domain (TD) AOCs [6]–[11] have demonstrated a superior speed to their voltage-domain (VD) SAR and pipeline counterparts thanks to the technology scaling. However, the metastability artifact of the TD ADC is often overlooked, which can be severe under a stringent time deadline and is worth great attention. In literature, TD circuits are often leveraged to facilitate the “metastability detector” [1], while the metastability events indeed cannot be detected because the detector itself can experience metastability. They often detect the error within the loop time, which therefore involves limited additional gain and decision time with extra load on the critical path, leading to a potentially diminished return on error probability <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{P}_{\mathrm{m}\mathrm{e}\mathrm{t}\mathrm{a}})$</tex>. Prior work [2], [3] decouples such constraints by pipelining the comparator decisions with additional latches, thus allowing extra gain and time on the detection. This proper unresolved-decision (UD) detection demonstrates an outstanding <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{P}_{\mathrm{m}\mathrm{e}\mathrm{t}\mathrm{a}}$</tex> in a time-interleaved SAR architecture [3]. However, it compromises latency with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{P}_{\mathrm{m}\mathrm{e}\mathrm{t}\mathrm{a}}$</tex>, which is feasible in SARs but not in multistep ADCs.

University of Macau (MO)
Openalex Percentile: Top 34%
Analog and Mixed-Signal Circuit Design
0.67
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24.4 A 10b 3GS/s Time-Domain ADC with Mutually Exclusive Metastability Correction and Wide Common-Mode Input — Chi–Hang Chan, Wei Zhang, et al. · (2025) | TGRS Research Map | TGRS