Optimization of D flip-flop in RFID reader using full swing gate diffusion input (FSGDI) with buffer circuit to improve power efficiency

CMOS technology, commonly used in RFID circuits, faces limitations in power efficiency and chip size. This study optimizes the D Flip-Flop in RFID readers using Full Swing Gate Diffusion Input (FSGDI) with added buffers to reduce transistor count, power consumption, and delay, enhancing system performance. FSGDI achieves a stable output voltage and the lowest power consumption of 32.74 μW, reducing power by 84.91% with a lower delay of 0.15 ns and 3.3 V compared to CMOS. The D-flip-flop with FSGDI integration proposed in this study is beneficial for improving power efficiency and signal stability in RFID readers.