MicroNAS for memory and latency constrained hardware aware neural architecture search in time series classification on microcontrollers

The use and research of neural networks on very small processor systems are currently still limited. One of the main reasons is that the design of microcontroller-architecture-aware ML models that take into account user-defined constraints on memory consumption and run-time are very difficult to implement. Therefore, we adapt the concept of differentiable neural architecture search (DNAS) to solve the time series classification problem on resource-constrained microcontrollers (MCUs). This paper explores and demonstrates for the first time that this problem can be solved using Neural Architecture Search (NAS). The key of our specific hardware-aware approach, MicroNAS, is an integration of a DNAS approach, Latency Lookup Tables, Dynamic Convolutions and a novel search space specifically designed for time series classification on MCUs. The resulting system is hardware-aware and can generate neural network architectures that satisfy user-defined limits on execution latency and peak memory consumption. To support our findings, we evaluate MicroNAS under different latency and peak memory constraints. The experiments highlight the ability of MicroNAS to find trade-offs between latency and classification performance across all dataset and microcontroller combinations. As an example, on the UCI-HAR dataset, MicroNAS achieves an accuracy of 94.62% when allowed 25 ms and 98.86% when allowed 50 ms when running on the Nucleo-L552ZE-Q. The much more powerful Arduino Portenta, on the other hand, achieves an accuracy of 95.88% with an allowance of 3 ms and 99.37% when allowed 25 ms displaying the ability of MicroNAS to adapt to different microcontrollers. MicroNAS is also able to find architectures which perform similarly to state-of-the-art systems designed to run on desktop computers (99.62% vs. 99.65% accuracy on the UCI-HAR dataset and 97.83% vs. 97.46% accuracy on the SkodaR dataset).