An Efficient FPGA Implementation of Wiener Filter

Wiener filter is one of the inevitable designs used in the signal processing applications. In this paper, we propose an efficient FPGA implementation of Wiener filter using dual core Zynq 7000 SoC with partial reconfiguration. The proposed implementation supports to perform two pipelined Wiener filter operations in parallel. The proposed implementation reduces the hardware resources as compared with various existing implemen-tations due to the partial reconfiguration. Similarly, the proposed implementation improves the reduction in latency due to parallel operations.