DLP Based Processing-in-Memory Architecture Leveraging Content Addressable Memory

Processing-in-Memory (PiM) is one of the rapidly growing paradigms in this world of computer architecture, wherein the data is processed and stored simultaneously within the memory. This architecture will enable us to perform big data computing that require complex data transitions between memory and ALU with reduced latency and improved throughput. This scheme utilizes the concept of Data Level Parallelism (DLP), to perform multiple operations with less number of clock cycle using a single instruction. In this paper, ALU operations such as addition, multiplication and logical operations are proposed using PiM with a single instruction by means of fixed memory locations. All the operations are implemented by the concept of Single Instruction Multiple Data (SIMD) techniques. The addition is implemented using the Parallel Adder (PA), while multiplication operations are implemented using the karatsuba multiplier. In this work, parallel addition can be implemented with a frequency of 1.42 GHz within the memory, while parallel multiplications can be implemented at a maximum frequency of 2.31 GHz for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times 2$</tex> bit multiplication by incorporating the karatsuba technique. These implementations consume maximum resources upto 121268 cells of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{NAND}2 \times 1$</tex> units when inferred in the form of logic cells. Post-layout implementation resulted in an area of area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$83.25 \ \mu m^{2}$</tex> for inferring a 1-bit CAM cell.