Performance Evaluation of PLL Frequency Synthesizer with 3-Stage and 7-Stage Current Starved VCO

This work performs a comparative investigation of the Phase Locked Loop frequency synthesizer (PLL-FS) with a 3-stage and a 7-stage Current Starved Voltage Controlled Oscillator (CS-VCO) using Cadence virtuoso platform with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{0.18}\boldsymbol{\mu} \mathbf{m}$</tex> CMOS technology for GSM and RF applications. The performance evaluation is done with the help of various parameters such as phase detector gain, VCO gain, frequency of oscillations, lock time, lock range, and power dissipation. The design incorporates a 3-stage or a 7-stage CS-VCO, a phase frequency detector (PFD), a tri-state charge pump, first order low pass filter, and a divide-by-16 circuit. The results suggest that PLL-FS with 3-stage CS-VCO could be a better choice than its 7-stage counterpart for natural frequency, lock time, lock range, power dissipation, and area considerations. In contrast, the PLL FS with 7-stage CS-VCO could be better than its 3-stage counterpart for gain and phase noise considerations.