A 28-nm 142-mW Motion-Control SoC for Autonomous Mobile Robots
Autonomous mobile robots (AMRs) have been proven useful in various applications. Motion control is essential for AMRs to adjust the trajectory, especially when AMRs are operated in a fast-changing environment. This work presents a motion-control system-on-chip (SoC) for AMRs that demand low response time and robust control. A sampling-based motion-control algorithm that enables highly parallel hardware acceleration is adopted. Trajectory pruning and physics model transformation are proposed to minimize the computational complexity. The SoC includes a trajectory optimization accelerator that consists of an array of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${4} {\times } {4}$ </tex-math></inline-formula> processing elements (PEs). The PE’s architecture is optimized for trajectory computations to reduce latency and memory usage. A network-on-chip (NoC) is designed for efficient data movements and workload balancing between PEs. An ARM Cortex-M3 microcontroller unit (MCU) is integrated into the SoC for system configurations and scheduling. Fabricated in a 28-nm CMOS technology, the chip has 3.56 mm2 core area. The chip dissipates 142 mW at a 200-MHz clock frequency from a 1.0-V supply. It achieves a 4935-Hz maximum motion-control rate for 130 trajectory time steps for a 7-degree-of-freedom (7-DoF) robot arm on an AMR. The SoC also delivers a 35-Hz/mW maximum energy efficiency. This work outperforms the state of the art, achieving a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$22{\times }$ </tex-math></inline-formula> higher maximum motion-control rate and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$35{\times }$ </tex-math></inline-formula> higher energy efficiency, at the same technology node.
Authors
- I-Ting Lin (ORCID: https://orcid.org/0000-0001-9025-9611)
- Nian-Shyang Chang
- Zih-Sing Fu (ORCID: https://orcid.org/0000-0003-4061-0404)
- Wen-Ching Chen
- Liang-Yi Lin
- Chi‐Shi Chen
- Chun‐Pin Lin (ORCID: https://orcid.org/0000-0002-3498-1113)
- Chia‐Hsiang Yang (ORCID: https://orcid.org/0000-0003-1163-321X)
Institutions
- National Taiwan University (TW)
- Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
Publication Details
- Journal
- IEEE Journal of Solid-State Circuits
- Published
- 2025-03-04
- DOI
- https://doi.org/10.1109/jssc.2025.3543621
- Primary Topic
- Embedded Systems Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00