Enhancing Analog Performance in Nanometer FinFET Technology: Bridging the Device-Circuit Co-Design Gap for Low-Power Applications

In modern electronics and communication systems, the major driving force have been primarily based on down-scaling the minimum transistor size according to Moore0 s law. Furthermore, the efforts to overcome limitations of planar technology have led to development of non-traditional architecture such as Fin shaped Field Effect Transistor (FinFET) and other Multigate devices to achieve compactness. A FinFET, self-aligned process is more resilient to short channel effects in nanometer technology node. In addition to the non-planar nature of multi-gate devices, several technology integration challenges such as the availability of compact model that need to be addressed before it can be accepted by circuit designers as a feasible technology. The Figure of Merit (FoM) of analog circuits is significantly influenced by the analog performance of the device technology. This proposed work endeavors to connect the device-circuit co-design gap that has severely improved circuits performance using emerging FinFET devices. Considering the nanometer FinFET device technology, an attempt is made to enhance the analog performance parameters by engineering the geometrical structure of FinFET device. The device structure is a three-dimensional (3-D) architecture of Silicon on Insulator (SOI) 12 nm FinFET with a high- K hafnium oxide as gate electrode operated in both strong inversion as well as weak inversion regime for low power and low voltage. To demonstrate the influence of the improved analog performance parameters of proposed device on circuit performance, it is integrated within analog circuits where low power dissipation is highly desired.