An Efficient Technique to Design Ternary Logic Schematics with Pseudo N-GNRFETs

Ternary systems are particularly appealing for nano-scaling design due to several benefits such as high density and quicker operation that may be realized with future technologies. This paper describes a unique ternary circuit that employs graphene-nanoribbon transistors (GNRFETs). For operation, pseudo N‑GNRFE-Ts are employed in the proposed inverters and universal gates. This method uses threshold voltages regulation of P and N transistors to ensure proper functioning of ternary logic circuits. When related to complementary-schematics, projected ternary designs improved power by 47.08%, delay by 38.95%, and power-delay-product (PDP) by 64.43%, respectively.