High Performance Poly-Si Vertical Trench Power MOSFET Using Double Charge Balance Technique: Design and Simulation

In this work, a new vertical power MOSFET (SJSGTPMOS) structure, using a double charge balanced technique, is proposed and designed for the first time. The double charge balance technique is achieved by splitting the Trench Poly-Si gate and converting the n-drift region into a stack of charge-balanced p/n pillars, which significantly improves the device performance and reduces the total requirement of gate charge as well as Gate-To-Drain Terminal Capacitive (Cgd) coupling. Using 2D-Silvaco ATLAS, the high-performance electrical characteristics output is achieved in our proposed device, compared with the conventional trench MOSFET. The proposed device gives excellent results of 0.94 pC Gate Charge (Qgd), 33.6% improvement in breakdown voltage, 74.1% and 99.29% improvements in two Baliga's Figure of Merits (FOM1 and FOM2), 91.62% in Cgd, at epilayer thickness of 1.2μm, showing the enhancement features of the proposed structure over the existing state-of-the-art, using two perfectly different charge balanced technique, without any impact on the gate control.