Exploring Efficient BCD to Binary Conversion Architecture Alternatives on FPGA

BCD operands are used in embedded systems and human-centric applications due to their ease of interpretation. To optimize arithmetic operations on hardware designed for binary inputs, BCD inputs must be converted to binary. This paper explores FPGA-specific logic primitives, such as dual output look-up tables (LUTs) and carry chains, to implement efficient parallel, serial, and pipelined architectures for BCD-to-binary conversion. Primitive instantiation was employed to directly configure FPGA elements, enhancing design efficiency and performance. Multiple adder tree implementations were examined which suggested trade-off between speed and area.