AI-Driven Power Gating for Enhanced Energy Efficiency in Superscalar Processors

Amid the rising demand for efficient processors, the challenge has always been to reduce power consumption without compromising performance. FinFET technology has significantly reduced leakage power issues, but dynamic power consumption at lower nodes has reemerged as a concern. Methodologies such as power/clock gating, DVFS, and voltage biasing have been proposed in the past. However, next-generation complex SoC designs at < 7nm technology require rethinking at finer granularity. The power gating methodology proposed by You et al., Roy et al., and PG-instr algorithm [1] reduce power consumption but have performance drawbacks. These techniques cause at least a 2% drop in performance in terms of wake-up latency. Moreover, You et al. and Roy et al. only considered idle time, while PG-instr focuses solely on energy savings. None of them balance idle time and energy savings together, which is crucial for achieving the best performance with low power consumption.