Impact of Constraint Modifications on the CRYSTALS-Kyber Hardware Design

The lattice-based post-quantum cryptography scheme is widely regarded as one of the most secure solutions to address the emerging threats posed by advancements in quantum computing. Various groups have analyzed and studied the hardware implementation of the CRYSTALS-KYBER design, and they continue to work on optimizing the design. Researchers have applied various techniques throughout the design to enhance power consumption, area utilization, and output speed. The main goal of this work is to present the impact of constraints on design performance, analyzing factors such as Worst Negative Slack (WNS) and total power. After introducing input and output delay constraints, we found that the actual operating frequency was 91.29 MHz, deviating significantly from the initially claimed 169.92 MHz.