CaH2:Criticality aware Hybrid L2

All dynamic instructions do not contribute equally for an application’s performance. The instructions that contribute majorly towards an application’s performance are said to be critical. Using instruction criticality, we designed a hybrid SRAM - STTRAM cache at the L1 level. The principle behind the hybrid cache was to place cache lines that will be mostly accessed by critical load instructions in the small and fast SRAM partition and the remaining cache lines in the large and slow STTRAM partition. The designed hybrid cache showed a performance gain of 6.1% when compared to a baseline system that uses only SRAM based cache of similar area, at a cost of 1.7% increase in the energy consumption by the private caches. In the current work, we present the scope available to design a cognate hybrid cache based on instruction criticality at the L2 level.