LiveWay: Dynamic Write Bypassing for Lifetime Enhancement in STT-RAM LLC

Next-generation workloads require Last Level Cache (LLC) to be fine-tuned for larger working sets and data-intensive on-chip operations. SRAM LLCs have large area and high leakage energy, while STT-RAM (Spin Transfer Torque) LLCs, offer non-volatility, low leakage power, high density, and better scalability. Despite its advantages, implementing STT-RAM LLCs remains challenging due to low write endurance and high write latency. The problem of low write endurance is enhanced by non-uniform write distribution across cache ways as depicted in Figure 1 . Non-uniform writes to the cache are the major reason for decreasing the lifetime of the STT-RAM LLC. Write variations in the STT-RAM LLC can be classified as: (i) Inter-set Write Variation (InterV) and (ii) Intra-set Write Variation (IntraV). InterV denotes the disparities in write distribution across different cache sets, whereas IntraV captures the fluctuations in write patterns within the individual blocks of each set. In order to combat the increasing write variation in the STT-RAM LLC various wear-leveling techniques have been proposed that aim to reduce both the InterV and IntraV.