Energy-efficient V<sub>aq</sub>-based switching scheme with bottom-plate sampling for SAR ADCs

A novel digital-to-analog converter (DAC) switching scheme has been developed to improve the power efficiency of successive approximation register (SAR) analog-to-digital converters (ADCs). This scheme involves sampling the input signals on the bottom-plates of the most significant bit (MSB) capacitors, effectively eliminating the reset energy. The reference voltage VREF is only switched during the third-bit cycle, avoiding more power consumption. Moreover, a one-sided two-level switching technique is utilized from the fourth-bit cycle onwards. As a result of this innovative switching approach, there is a 66.97% reduction in switching energy compared to the method proposed by Sanyal. The post-layout simulation results demonstrated that the proposed SAR ADC achieves the ENOB of 9.68 bits at a sampling rate of 20 KS/s, and consumes 36.9 nW of power in a 0.18-μm 1P6M CMOS process with a 0.6 V power supply, resulting in a figure of merit (FOM) of 2.25 fJ/conversion-step.