ADC bandwidth doubler with Nyquist-rate sampling in analog-digital hybrid equivalent ideal filter

This paper proposes a novel analog-to-digital converter (ADC) bandwidth doubler with Nyquist-rate sampling in analog-digital hybrid equivalent ideal filter (ADH-EIF). The ADH-EIF enables the required analog bandwidth of the sub-ADCs to be a half of the overall bandwidth of the frequency doubler by using analog mixers for wideband quadrature downconversion. In the bandwidth doubler the sample-and-hold (SH) circuits of the sub-ADCs in an ADH-EIF sample the down-converted signals at the peaks of the quadrature carriers at Nyquist rate. After that, zeros are inserted by upsampling in the digital domain. As a result, the output waveforms coincide with the ones of the oversampled signals in an ADH-EIF we reported previously. This means that the proposed doubler reduces the sampling rate at SH circuits by a factor of two. This reduction of the sampling rate is advantageous in mitigating the requirements for the sampling clocks on jitters. A circuit simulation shows a good fundamental signal transmission performance of the doubler for power spectral density and an eye pattern with a PAM4 signal.

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Publication Details

Journal
IEICE Electronics Express
Published
2025-03-02
DOI
https://doi.org/10.1587/elex.22.20250058
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
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article

ADC bandwidth doubler with Nyquist-rate sampling in analog-digital hybrid equivalent ideal filter

K. Ihara, Kyoya Takano, Yohtaro Umeda
IEICE Electronics Express
Analog and Mixed-Signal Circuit Design
article

ADC bandwidth doubler with Nyquist-rate sampling in analog-digital hybrid equivalent ideal filter

K. Ihara, Kyoya Takano, Yohtaro Umeda
article en

Abstract

This paper proposes a novel analog-to-digital converter (ADC) bandwidth doubler with Nyquist-rate sampling in analog-digital hybrid equivalent ideal filter (ADH-EIF). The ADH-EIF enables the required analog bandwidth of the sub-ADCs to be a half of the overall bandwidth of the frequency doubler by using analog mixers for wideband quadrature downconversion. In the bandwidth doubler the sample-and-hold (SH) circuits of the sub-ADCs in an ADH-EIF sample the down-converted signals at the peaks of the quadrature carriers at Nyquist rate. After that, zeros are inserted by upsampling in the digital domain. As a result, the output waveforms coincide with the ones of the oversampled signals in an ADH-EIF we reported previously. This means that the proposed doubler reduces the sampling rate at SH circuits by a factor of two. This reduction of the sampling rate is advantageous in mitigating the requirements for the sampling clocks on jitters. A circuit simulation shows a good fundamental signal transmission performance of the doubler for power spectral density and an eye pattern with a PAM4 signal.

IEICE Electronics ExpressVol. 22(8)
Tokyo University of Science (JP)
Affordable and clean energy
Openalex Percentile: Top 96%
Analog and Mixed-Signal Circuit Design
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ADC bandwidth doubler with Nyquist-rate sampling in analog-digital hybrid equivalent ideal filter — K. Ihara, Kyoya Takano, et al. · IEICE Electronics Express (2025) | TGRS Research Map | TGRS