WITHDRAWN:A Read Delay Compensated and Write Assist Sram Cell with Power Gated and Power Delay Product Reduction Circuitry

The main highlights of this work are, • To design an half select disturb free write assist (HDFWA) SRAM cell with power delay product reduction circuitry(HDFWA-PDP). • To build a compensation-based sensor circuit in the SRAM cell to reduce the leakage current and speed up read operation. • To reduce the power dissipation of the proposed HDFWA-PDP cell, the power delay product (PDP) reduction circuitry with a power gating mechanism is introduced. • Propose a low-power and ultra-fast offset compensated sense amplifier to increase the sensing margin. Low-power static random access memory (SRAM) isin high demand foritspower-efficient neural network inference engine requirement. This study proposes a new Half-Select Disturb-Free Write Assist (HDFWA) SRAM cellwith 9 transistors. The HDFWA-SRAM cell is designed with a delay product reduction (PDP) circuit. The proposed SRAM design uses a compensation-based sensor circuit to reduce the leakage power and enhance read performance. The sensor detects the voltage drop generated by the leakage current. The compensation circuit is activated as soon as the leakage is detected. The proposed cell will be able to address the column (row) half-selection issue by optimizing the read static noise margin (RSNM) and write static noise margin (WSNM).The PDP comprises an adaptive voltage detector (AVD) and pass-transistor gate voltage boost (PVB). This PDP minimization strategy increases the efficiency of read/write operations by choosing a low supply voltage for the idle cells. Overall, the prior designs failed to find a reasonable balance between power consumption efficiency and time used for sensing. This study proposes a high-speed, low-power sense amplifier with an offset compensation approach to boost the sensing margin. The simulation results are compared with existing designs such as SEDF10T, SBL9T,TG8T and TS14T to demonstrate the better performance of a proposed work. The suggested SRAM cell outperforms the state-of-the-art SRAM cells in terms of read access time (RAT), write access time (WAT), static noise margin (SNM) analysis and power analysis.