Structural design of memory system for Ternary Optical Computer

Ternary Optical Computer (TOC) is unique in the development of optical computers, in terms of principle, experiment, algorithm and application. After 20 years of development, six generations of prototypes have been developed. At present, tri-state optical signal storage is the main problem faced by TOC. According to the characteristics of tri-state optical signals and the ternary optical processor's special requirements for storage systems, we design and implement the interface structure of TOC memory system, including the overall structure of the interface, the address generation module for memory access, the data input and output channels, the read/write timing, and the working process of the memory interface. Finally, the correctness of the memory system interface design is verified by the experiments, which are carried out on FPGA, of reading and writing operational result data of the SD16 TOC prototype. This work tries to improve the theoretical system and practical basis of TOC.

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Publication Details

Journal
PLoS ONE
Published
2025-02-28
DOI
https://doi.org/10.1371/journal.pone.0309839
Primary Topic
Optical Network Technologies
Type
article
Field-Weighted Citation Impact
0.00

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Structural design of memory system for Ternary Optical Computer

Zhehe Wang, Xunlei Chen, Shan Ouyang, Hongjian Wang et al.
PLoS ONE
Optical Network Technologies
article

Structural design of memory system for Ternary Optical Computer

Zhehe Wang, Xunlei Chen, Shan Ouyang, Hongjian Wang, Shuang Li, Y. Jin, Honghong Zhang
article en

Abstract

Ternary Optical Computer (TOC) is unique in the development of optical computers, in terms of principle, experiment, algorithm and application. After 20 years of development, six generations of prototypes have been developed. At present, tri-state optical signal storage is the main problem faced by TOC. According to the characteristics of tri-state optical signals and the ternary optical processor's special requirements for storage systems, we design and implement the interface structure of TOC memory system, including the overall structure of the interface, the address generation module for memory access, the data input and output channels, the read/write timing, and the working process of the memory interface. Finally, the correctness of the memory system interface design is verified by the experiments, which are carried out on FPGA, of reading and writing operational result data of the SD16 TOC prototype. This work tries to improve the theoretical system and practical basis of TOC.

PLoS ONEVol. 20(2)
Shanghai University of Engineering Science (CN), Donghua University (CN), Shanghai Normal University (CN), Henan University of Economic and Law (CN)
Innovative Research Group Project of the National Natural Science Foundation of China, Natural Science Foundation of Hainan Province, Fundamental Research Funds for Central Universities of the Central South University
Quality Education
Openalex Percentile: Top 97%
Optical Network Technologies
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