A 64 dB-DR, 4.5 GHz-BW Logarithmic Amplifier for RSSI Measurement in 180 nm SiGe Process

For RSSI measurement of RF systems, a wide band, large dynamic range (DR), parallel-summation logarithmic amplifier is presented in this paper. The circuit adopts an 8-stage DC-coupled cascaded limiting amplifier structure. The output voltage of the limiting amplifier is converted into current through a rectifier to realize parallel summation. In order to reduce offset, this paper introduces offset reduction circuits in the gain and output stage, respectively. In addition, a log slope adjuster is proposed, which can achieve log slope control of different frequency inputs. The post-simulation results show that at a power supply voltage of 5 V, the 3 dB gain bandwidth is 4.5 GHz, the dynamic range reaches 64 dB, and the log error is less than ±1 dB. The overall circuit consumes 21 mA of current.