Performance Optimization of Silicon Nanowire MOSFETs for Next-Generation Low Power Applications

This paper presents performance optimization of Silicon-Nanowire-Metal-Oxide-Semiconductor-Field-EffectTransistors (Si-NW-MOSFETs). As the semiconductor industry progresses toward smaller and more efficient device dimensions, the advantages of silicon nanowire MOSFETs have become increasingly prominent. Si NW MOSFETs are positioned as key candidates for future integrated circuit technologies, owing to their exceptional attributes, including high on-current and minimal leakage current. This study establishes crucial parameters at a gate voltage of 1.5 V and a drain voltage of 1 V: Sub-threshold Swing ($\mathrm{SS}=\mathbf{6 6 ~ m V} /$ decade), Leakage Current ($l_{\text {off }}=1 \mathbf{p A} /\mu \mathrm{m}$), Threshold Voltage $V_{\text {th }}=0.346 \mathbf{V}$, On Current ($\left(I_{o n}=14 \mu \mathrm{~A} / \mu \mathrm{m}\right)$, On/Off Ratio ($\frac{10 n}{\text { Ioff }}=10^{7}$), and Trans-conductance ($\mathrm{g}_{m}=800 \mu \mathrm{~S} / \mu \mathrm{m}$). Results indicate marked enhancements in drive current and sub threshold slope when compared to traditional MOSFETs, underscoring the potential of nanowire configurations to address future scaling challenges.