FIPLib: An Image Processing Library for FPGAs Using High-Level Synthesis

Abstract This paper investigates the use of High-Level Synthesis (HLS) for designing parallel hardware architectures on FPGAs. HLS compilers, like the one used in Vitis HLS, extract the available parallelism so the HLS languages should be thought as inherently parallel and should be programmed with the target parallel architecture in mind. We discuss how HLS facilitated the development of FIPLib, an image processing library for FPGAs, leveraging the streaming model. This library comprises parallel kernels connected through streams to implement a streaming data-flow computation. Following an overview of the library’s functionalities and its parallel implementation, we present the benefits of adopting this FPGA library, particularly in terms of speed and power consumption. We conduct a comparative analysis by implementing two image processing algorithms using both our FPGA library and the equivalent OpenCV CPU and GPU implementation. The results demonstrate that FPGAs programmed through FIPLib can significantly accelerate computations and/or reduce power consumption.