A holistic lithography approach to wafer edge overlay control

To secure a high number of yielding dies in the production of the advanced semiconductor nodes, the on-product overlay (OPO) performance must be kept within tight specifications across the full wafer. With increasing shrink on the advanced nodes, this task becomes even more challenging especially close to the wafer edge. This is since, by design, the wafer processing is not as well-controlled close to the wafer edge as the center of the wafer [1]. To secure the OPO performance close to the wafer edge, besides adopting advanced processing techniques, it is important to utilize the capabilities of the holistic lithography system to monitor and control the overlay performance [2]. In this paper, we demonstrate how holistic lithography can be utilized to detect and correct the contributing factors to overlay degradation close to the wafer edge and to secure high performing chips on the full wafer. Two layers from the node R&D phase, namely A and B, with degraded OPO performance in the region of 135-145mm, hereafter referred to as the wafer edge region, were investigated. Dense After Develop Inspection (ADI) metrology data as well as scanner wafer alignment data over multiple lots were used in our study. The data, for layers A and B respectively, showed more than 100% and 90% worse performance at the wafer edge region compared to the inner part of the wafer for the critical direction. We investigated holistic lithography solutions to control the wafer edge region OPO into spec by using the scanner monitoring and control loop and its correction potentials. We applied the identified corrections on the overlay in a Run-to-Run (R2R) control simulation setting. The simulation results show an improvement of about 21% and about 28%, for layers A and B respectively, on the wafer edge overlay performance. These improvements come at no cost to the measurement load and the wafers per day. Evaluations to verify the in-resist performance for both layers are ongoing. The initial in-resist self-correction evaluations on layer B suggests about 15% improvement at the wafer edge region.