Efficient Design and Implementation of Conditional Full Adder-Based Truncation Multipliers for High-Performance Applications

This paper presents a novel approach to designing high-performance, low-power truncation multipliers by utilizing a conditional Full Adder (FA) circuit. The proposed design simplifies traditional FA structures using a combination of multiplexers and XOR gates to reduce power consumption, area, and delay without compromising computational accuracy. The proposed FA design was integrated into truncation multipliers and evaluated against existing designs, including conventional, almost, and approximate Full Adders. Comparative analysis reveals that the proposed design achieves a 23.8% reduction in area, a 16.7% improvement in delay, and a 30% reduction in the power-delay product (PDP) compared to conventional designs. These enhancements are demonstrated through FPGA and ASIC implementations, achieving superior performance for 16-bit and 32-bit multipliers in terms of LUT utilization, power efficiency, and speed. The proposed architecture is particularly suited for applications in signal processing and embedded systems, where energy efficiency and high-speed computation are critic.