Accelerated Extraction of Parasitic Capacitance in Metal Interconnects using Floating Random Walk Method

This paper presents a novel and efficient approach for the rapid extraction of parasitic capacitance in metal interconnects of large-scale integrated circuit (IC) layouts. By conducting detailed electromagnetic field simulations, we propose a streamlined method that significantly reduces both computational complexity and runtime, making the extraction process more efficient. At the heart of this approach is the use of the floating random walk (FRW) algorithm, which precisely estimates both self-capacitance and mutual capacitance of conductors. A distinguishing feature of this method is the incorporation of error thresholds, which provide a dynamic mechanism to adjust the trade-off between extraction speed and accuracy. This flexibility allows the method to adapt to varying layout complexities while maintaining a high level of precision. Experimental results reveal that, compared to traditional electromagnetic simulation tools such as ANSYS Maxwell, the proposed method achieves up to 120 times faster capacitance extraction, with accuracy deviations containedwithin 20%.