Design of Pseudo-LFSR Based Physical Unclonable Function

Physical Unclonable Functions (PUFs) are primarily used for authenticating hardware devices. The objective of this research is to generate a large set of challenge-response pairs to strengthen the PUF. The Pseudo-LFSR PUF design relies on LFSR but does not contain any shift register; instead, it employs combinational circuits like inverters and XOR gates. The PUF's strength is based on the quantity of challenge-response pairs it possesses, with a larger set indicating better security and authentication. The proposed PUF has significant advantages, such as producing a large-bit response, with n bits of response captured from a single n-bit challenge. Moreover, the mapping of challenge and response pairs can be varied without disrupting the hardware structure. Typically, Physical Unclonable Functions are implemented on FPGAs and ASICs. This study discusses the detailed design of a strong LFSR-based PUF and how the modified design increases the challenge-response pairs.