Two-Phase Transistor Sizing for FPGAs via Bayesian Optimization

Transistor-level design is pivotal for the accurate evaluation of FPGA architectures. Since traditional linear models are increasingly inadequate in advanced technology nodes, simulation-driven approaches have become the standard for FPGA architecture exploration. However, due to the non-analytical nature of delay measurements from simulations, the transistor sizing process becomes a black-box optimization problem. COFFE2 [1], [2], the state-of-the-art academic sizing tool employs a division-based brute-force approach, which is relatively time-consuming and may lose optimal solutions. In this paper, we propose a two-phase transistor sizing methodology and enhance the COFFE2 framework with Bayesian Optimization, which is well-suited for black-box optimization problems. Our proposed approach not only achieves a 11.7% improvement in the quality of results but also reduces runtime by ~40%-70%. Through extensive benchmarking on a complete design flow, from transistor-level sizing to routing with VTR benchmarks, we demonstrate that FPGA architectures optimized by our approach offer an 11.0% reduction in the area-delay product, proving the efficacy of our method.