Measuring the Minimum Power Requirement of FPGA Architectural Specifications

Bypass capacitances bridge the gap between momentary surges of power demand caused by switching transistors and the ability of power supplies to respond to these surges. Even though bypass capacitances are not explicitly specified in FPGA architectural specifications, the gate capacitances of quiescent transistors in an FPGA architecture can act as symbiotic bypass capacitances. Since any additional dedicated bypass capacitances can increase the implementation area of an FPGA, it is important to measure the ability of the quiescent bypass capacitances in maintaining stable operating voltages while the FPGA is powered by voltage sources with limited power outputs. This work measures the ability of the quiescent bypass capacitances in maintaining stable supply voltages under limited power in the context of FPGA architectural investigations. We found that, for the 12-LUT logic cluster investigated in this work, to limit VDD value droop to 5% of the nominal VDD value, the power source must be able to produce 3 times of the average power consumed by the same logic cluster powered by an ideal voltage source. When the power output is further reduced, VDD value droop increases, resulting in significantly increased delay and reduced noise margin. In addition, the degree of parallel execution also has a significant effect on VDD value. In particular, at the nominal VDD value of 0.9 volts and the maximum power output of 28.1 uW, executing all 12 LUTs in parallel results in VDD value drooping to a minimum value of 0.370 volts while executing 1 LUT at a time results in VDD value drooping to a minimum of 0.690 volts, with both cases achieving similar computing time. These results suggest that FPGA architectural evaluations should take bypass capacitances and the power limit of voltage sources into consideration in order to design efficient FPGA architectures for low power applications.