PipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis

High-level synthesis (HLS) has received significant interest in hardware accelerator design due to its ability to reduce design time and make hardware design more accessible to software developers [3]. HLS methodologies can be categorized into two main approaches: statically scheduled HLS [2, 4] and dataflow HLS [5, 6]. Statically scheduled HLS requires precise operator delay information at synthesis time to generate optimized schedules, which often lead to suboptimal performance under dynamic workloads. In contrast, dataflow HLS maps programs into dataflow circuits composed of concurrent, independent elements that communicate using local control protocols (e.g., handshake or ready/valid). While dataflow HLS enables automatic pipelining without requiring global control, the lack of centralized coordination complicates efficient resource sharing.