Enhanced On-Chip Memory Reliability for Space Engineering using a Novel 2-Dimensional Error Detection and Correction Scheme

The paper presents a novel error detection and correction (EDAC) scheme tailored for space engineering applications, which aims to enhance the reliability of on-chip memory under challenging environmental conditions, including cosmic radiation and extreme temperatures. The proposed 2-dimensional code employs a divide-symbol strategy, utilizing XOR operations to encode diagonal, parity, and check bits during the encoding process. The decoding process is sophisticated, incorporating syndrome calculation and region selection to effectively identify and rectify errors. Simulation results obtained using Xilinx Vivado demonstrates that the proposed scheme achieves low power consumption and minimal area utilization compared to existing methods. Specifically, the encoder exhibits a maximum and minimum delay of 128 endpoints, with resource utilization metrics showing 0.02% LUT, 0.03% FF, and 25% IO utilization. The decoder exhibits a maximum and minimum delay of 64 endpoints, with resource utilization metrics of 0.03% LUT, 0.02% FF, and 19% IO utilization. This innovative EDAC methodology offers a promising solution for improving memory reliability in space applications, particularly by addressing issues caused by multiple cell upsets induced by radiation. The scheme's advantages, including enhanced memory reliability, reduced power consumption, and minimal area utilization, position it as a potentially valuable tool for future space engineering projects.