Customized Binary Convolutional Neural Networks and Neural Architecture Search on Hardware Technologies

Customized binary convolutional neural network (BCNN) architectures, which are implemented on hardware technologies, give significant advantages for computational efficiency and hardware acceleration. The deployment of these customized BCNNs in several real‐time domains such as edge devices, embedded systems and other resource‐constrained hardware platforms is becoming increasingly important. BCNN architectures, with their simplified representation of binarized weights and activations, significantly reduce computational and memory bandwidth requirements. On the one hand, the straightforward binarization of full precision CNN architectures achieves the hardware simplification. On the other hand, the binarization process suffers from the reduction in the algorithm performance. It would be highly desirable to improve the computational efficiency of the BCNN architectures through algorithmic and hardware‐level optimizations without significantly affecting the algorithm performance for implementation on hardware technologies. The usage of the neural architecture search (NAS) to optimize the BCNN architectures is becoming a promising approach. This paper proposes and illustrates efficient designs and customized BCNN architectures with examples for two edge applications (compressed sensing and image super‐resolution). Our designs improve the computational efficiency of the BCNN architectures through algorithmic and hardware‐level optimizations without significantly affecting the algorithm performance. In some cases, the NAS-optimized BCNN architectures perform better than the full precision CNN architectures. Hardware analysis substantiates the computational effectiveness of the proposed architectures.