Stability Analysis and Real-Time Optimization of a Power Hardware-in-the-Loop Setup

Power-Hardware-in-the-Loop (PHIL) is a powerful tool for studying the behaviour between a real Hardware under Test (HuT) and a simulated network. The real HuT can thus be tested for different scenarios via a power amplifier and measurement feedback in a closed control loop under safe laboratory conditions. Due to dead times in the control loop and numerical oscillations, instabilities can occur in a PHIL setup. In addition, the stability strongly depends on the ratio between the impedances of simulation and HuT. First, a theoretical investigation of the stability limits of a PHIL setup with the Ideal Transformer Method (ITM) is done, and the effects of dead times, power amplifiers, and impedances are discussed. The paper presents the actual lab-based PHIL setup and compares the theoretical stability limits with the measured values. The influence of the cut-off frequency of a Feedback Signal Filter (FSF) is explained. Control methods are introduced that adjust the cut-off frequency in real time in response to impedance variations, ensuring the stability of the PHIL setup while operating at maximum bandwidth. A two-point controller and a proportional controller are implemented and evaluated with a sinusoidal load and a switching load.