Method for Yield Enhancement of ReRAM Memory Arrays via Reference Voltage Calibration

This work proposes an adaptive reference voltage trimming algorithm for yield improvement of ReRAM memory arrays. The proposed method allows calibrating the reference voltage for each die individually post-fabrication, thus, miti-gating die-to-die variability that ReRAM is notorious for. It is shown that by trimming the reference voltage to the intersection point of data ‘1’ and data‘0’, the die yield can be significantly boosted for a given process technology and array specifications.