Effects of Cell Aspect Ratio and Applied Pulse Parameters on Resistance Drift in Ge₂Sb₂Te₅ PCM Nanodevices

The upward resistance drift in the amorphous phase of phase change memory (PCM) is one of the major hindrances to reliable device operation. Resistance drift is still not well-understood and is debatably linked to various physical mechanisms. Hence, further device characterizations on the impact of different factors are crucial to overcome the technological hurdles and clarify the underlying processes. In this work, we performed electrical characterization of capped Ge2Sb2Tes PCM line cells to evaluate how the cell aspect ratio and applied pulse parameters influence resistance drift and data retention trends. We observed that narrower embedded PCM cells have larger drift exponents than wide cells with similar programmed resistances, possibly due to higher internal stress and slower stress relaxation of the mechanically more confined amorphous zone of the narrow cell. This finding indicates the scaling challenge of embedded cells, which is not experienced by the uncapped cells. We also found that PCM cells programmed with repeated pulses exhibited the lowest drift exponents. Additionally, shorter rise and fall times resulted in lower drift exponents due to the minimal nucleation chances during the sharp falling edges, reducing the crystallization-induced stress. Thus, repeated sharp-edged programming pulses are the most energy-efficient and effective in suppressing the upward resistance drift compared to a single reset pulse. We also conducted thermally accelerated crystallization experiments at 400 K and found the wide cells to drop resistance slowly at the beginning compared to narrow cells, while all cells reached similar final resistance values and crystallized in a similar timeframe. Hence, scaling of embedded cells was not found to limit the long-term data retention time in PCM.