Quantum Circuit Optimization Via Graph Partitioning by Quantum Annealing

In quantum computing hardware, physical limitations are defining the connectivity of qubits, with Linear Nearest Neighbor being a convenient ordering for quantum mapping. To make quantum circuit Linear Nearest Neighbor-compatible, significant overhead (given by the so-called Nearest Neighbor Cost) may be caused by a set of additional gates necessary to make qubit lines of each gate of the circuit adjacent. In this work, the problem of quantum circuit optimization for Linear Nearest Neighbor architecture according to Nearest Neighbor Cost is treated by global qubit lines reordering. Such a reordering may be obtained as a result of graph partitioning heuristics. In this paper, we perform recursive graph partitioning on a quantum annealing hardware, thus making use of quantum optimizer to optimize a quantum circuit, to the best of our knowledge, for the first time. Extensive numerical experiments are performed for several circuits from various quantum circuit libraries, which demonstrate perspectives of the proposed approach.