Design of compact and high-performance SRAM cell in QCA technology for next-generation memories

Abstract The most significant high-speed memory used in random access memories (RAMs) is static random-access memory (SRAM). SRAM is fast and robust but confronts design issues in sub-nanoscale complementary metal oxide semiconductors (CMOS), including leakage current, area, and stability. A different technology that can be utilized as an alternative to overcome the limitations of traditional SRAM is Quantum-dot Cellular Automata (QCA) technology. In this work, a QCA-based SRAM cell is implemented using three 3-input majority gates and an inverter which significantly improves the minimal waste area, layout area, overall cell counts, QCA cost, and the clock delay (latency). The layout has 25 cell counts with an SRAM cell size of 0.02 μm 2 and a clock latency of 0.5 phases. Compared to a standard existing design, our proposed circuit achieves an improvement of 76% in cell counts, 84.6% in SRAM cell area, and 98.7% in QCA cost, demonstrating its potential for cost-efficient applications in modern electronic devices.