Implementation of An Ultra-Low-Power High-Speed CLB Using A Memory Element And Its Power Dissipation Analysis for FPGA with Quantum-dot Cellular Automata

Quantum-dot Cellular Automata (QCA) was popular due to its very low power consumption and fast operating speed. QCA Designers are fascinated with developing and implementing nanoscale devices of digital circuits with rapid operating speed, low power consumption, and less area requirement. This paper describes an efficient layout design of CLB for FPGA implemented using Lookup Tables (LUTs) constructed by using efficient Multiplexers and DFF. A 4-input LUT is implemented using 2x1 multiplexers, and D Flip Flop is incorporated into the LUT to frame CLB. Programmable routing resources for signal propagation and control are done by quantum cells. The proposed D Flip Flop was implemented with an area-efficient and less delay requirement. The functionality of the D Flip Flop in the CLB was analyzed using the simulation results of the QCA Designer tool. It is implemented with 53 quantum cells in a small area of 0.07µm2 and a delay of one clock cycle. Furthermore, the flexible logic block developed using the proposed D Flip Flop structure has proven to be the best among existing modules. The CLB architecture has 655 quantum cells spread across 1.32 µm2 with three clock cycles delay and a power dissipation of 43. 33nW. It is clear that the present is a better and more effective solution in terms of area, complexity, cell count, and latency. The QCA Pro and QCA Designer software is used for all designs and simulation results.