Design Method of Power Chip Terminations With Lower Cost, Lower Voltage Standing Wave Ratio, and Broader Bandwidth

ABSTRACT In this paper, we deeply explore a design method for power chip terminations with low‐cost, low VSWR and broadband performance. Through a comprehensive investigation of existing power chip terminations, the electromagnetic leakage significantly impacts its performance. To address these issues, an electromagnetic constraint boundary has been introduced to enhance its VSWR. Considering the high cost of the gold plating process on the sides of chemical vapor deposition diamond substrates, an independent electromagnetic constraint metal carrier with a concave shape is proposed. TaN thin film is employed as the terminal matching load. Simulation results reveal that the VSWR of different substrates (ceramic and diamond substrates) are very similar. Consequently, this work presents a design, simulation, and measurement of a power chip termination applied to a ceramic substrate. Measurement results demonstrate that the VSWR is less than 1.5 over a frequency range of DC to 43.5 GHz, significantly outperforming existing commercial power chip terminations. In addition, the fluctuation of VSWR across the broadband operating frequencies has been discussed in detail.