An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing

Analog compute in memory (CIM) with multilevel cell (MLC) resistive random access memory (ReRAM) promises highly dense and efficient compute support for machine learning and scientific computing. This article introduces analog to digital converter (ADC)-assisted bit-serial processing for efficient, high-throughput compute. Bit-serial digital to analog converters (DACs) and 8-bit binary-weighted multicycle sampling (BWMCS) ADCs perform analog vector-matrix multiplication (VMM) on MLC-based crossbar arrays. A direct drive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g}_{m}$ </tex-math></inline-formula>-boosted transimpedance amplifier (TIA) enables high-speed crossbar readout. We present a system on chip (SoC) prototype consisting of four self-contained ReRAM-based CIM macros and a reduced instruction set computer-five (RISC-V) host. The test chip is fabricated in 65 nm CMOS with foundry-integrated MLC ReRAM. We trained LeNet1 for handwritten digit classification and mapped the CNN weights differentially to 3-bit MLC ReRAM across multiple CIM macros. The classification accuracy loss is 1.6% when compared to the quantization-aware trained model. The measured raw and normalized peak efficiencies are 20.7 and 662 TOPS/W, respectively. The compute density is 8.4 TOPS/mm2.