Analytical Modeling of Oppositely Doped Core‐Shell Junctionless Nanowire Transistor Considering Fringe Capacitance and Dual Material Gate

Abstract This paper presents a physics‐based analytical solution for junctionless nanowire field effect transistor (JL‐NWFET) incorporating an oppositely doped core‐shell (ODCS) structure, dual material gate (DMG), and a high permittivity spacer by solving Poisson's equation. The surface potential concept has been used to derive threshold voltage, drain‐induced barrier lowering, drain current, and subthreshold slope. The results demonstrate that the cumulative benefits of ODCS, DMG, and high permittivity spacer in conventional JL‐NWFET enhance the device performance and mitigate short channel effects (SCEs). Furthermore, the close agreement between the analytical and simulation results for different core thicknesses, spacer permittivities, channel lengths, and channel thicknesses highlights the robustness and reliability of the proposed modeling methodology, offering valuable guidance for device optimization and design refinement in nanoelectronics applications.