Method for reducing false positives using pattern binning based on unsupervised learning

Semiconductor inspections face the challenge of maintaining high sensitivity for detecting defects while minimizing false positives. Distinguishing small defects from manufacturing variations such as line edge roughness becomes increasingly difficult as process shrinking continues. To effectively address this challenge, it is essential to adjust the detection sensitivity in accordance with the characteristics of the circuit pattern. We have developed a method for classifying circuit patterns using unsupervised segmentation techniques applied to SEM images. This approach enables automatic discrimination of areas such as memory cell regions and peripheral circuit pattern regions without requiring design data. By adjusting the sensitivity depending on the pattern region, the proposed method is able to reduce false positives by over 90% for memory devices.