Optimization of defect detection sensitivity and cost of ownership reduction in nano imprint lithography through design for inspection and advanced optical inspection

Photolithography is fundamental to semiconductor manufacturing, but as integrated circuits continue to shrink, the associated complexity and costs have escalated, particularly with the introduction of High Numerical Aperture Extreme Ultra-Violet (HNA EUV) systems. Nano Imprint Lithography (NIL) offers a compelling alternative, delivering a significantly lower Cost of Ownership (CoO) by physically imprinting nanometer-scale patterns into the resist, unlike traditional photolithography, which relies on light exposure. However, achieving robust process control and maintaining tool health in NIL requires a meticulous approach to Lithography Process Qualification (LPQ). This study investigates the integration of advanced Deep Ultra-Violet (DUV) Brightfield (BF) Optical Inspection technology with Stack Optimization to enhance a LPQ recipe for a 1xnm NIL line-space pitch stamp. Central to our methodology were Finite-Difference Time-Domain (FDTD) simulations, which played a critical role in identifying and selecting the most effective underlayer, material and thickness, to maximize defect detection sensitivity. Various optimization layers, strategically placed between the Silicon substrate and the resist adhesive layer were systematically tested on printed wafers. The maximum detection of the yield-critical Line Cut defects was achieved, in line with the predictions from FDTD simulations, surpassing the required success criteria for capture rate. This study not only demonstrates the effectiveness of the Design for Inspection (DFI) approach but also shows how optimizing the stack layers can reduce CoO for NIL process while improving defect control and yield in NIL-based processes. By integrating DFI principles with cutting-edge inspection techniques, this research outlines a clear pathway for achieving tighter defect control, higher yield, and enhanced process reliability in advanced semiconductor manufacturing.