Optimizing EUV OPC runtime and pattern fidelity in DRAM manufacturing using memory OPC flow

In DRAM (Dynamic Random-Access Memory) manufacturing, critical layers such as the high-density capacitor hole array and the bit-line periphery (BLP) with Storage Node Landing Pad (SNLP) pose significant challenges due to their complex patterning requirements. The capacitor hole array is crucial for DRAM performance, while the BLP layer involves intricate bi-directional line/space (L/S) designs. As DRAM technology transitions to EUV (Extreme Ultraviolet) lithography, single exposure solutions are sought to replace multi-mask processes, introducing challenges in maintaining resolution and reducing patterning time. In EUV processes, conventional Optical Proximity Correction (OPC) methods face a major bottleneck with excessively long runtimes, particularly in high-density array structures, which prolongs design cycles and increases manufacturing costs. This paper addresses the runtime issue encountered in EUV OPC by introducing a memory-optimized OPC flow, specifically designed to reduce computation time while preserving pattern fidelity. By leveraging memory structure characteristics and advanced computational techniques, we optimize the EUV mask simulation process and significantly reduce OPC runtime. This study explores how the method enhances pattern accuracy and shortens processing time in critical DRAM layers, particularly the capacitor hole array and bit-line periphery layers. Additionally, we investigate EUV-specific effects such as thru-slit and flare effects in memory data handling, which introduce further complexities in the patterning process. Experimental results indicate that the memory OPC flow not only resolves the long runtime issues of EUV OPC but also maintains high patterning accuracy, providing a reliable foundation for future DRAM manufacturing.