Overlay and wafer stress control in semiconductor manufacturing

In a continuous effort to scale bit cost despite the slowdown in lateral scaling, the semiconductor industry has shifted its focus towards vertical scaling leading to high aspect ratio (HAR) devices. Notably, memory devices, such as 3DNAND, have experienced significant vertical scaling, and it is anticipated that DRAM will follow suit with the introduction of 3DDRAM. The growth in the Z direction has led to the adoption of stacks of multi-layer thin films followed by patterning and etching of HAR features. In the 3DNAND device, the most critical etch is that of the channel hole which is essentially a string of channels in the vertical direction that forms the core of the NAND cell. Ensuring good channel hole profile control through the entire cell string is achieved by building the device in a number of tier stacks. Etching each tier stack is accomplished using hard masks with excellent selectivity to the underlying film stack. However, such high selectivity hard masks impart a high level of stress to the wafer – the resulting warp is made worse by subsequent etching of the underlying stack which relieves stress locally and causes local variations in Out of Plane Distortion (OPD). This OPD results in an In Plane Distortion (IPD) which affects the device overlay. This paper presents a technique that enables simultaneous control of wafer shape and overlay by utilizing a stress compensation layer (SCL) and selectively modifying the stress within the SCL using a localized energy source. The paper outlines the key performance indicators (KPIs) used to evaluate the effectiveness of this technique in high volume manufacturing (HVM). The proposed approach addresses both the chuckability of wafers in downstream processing (critical for ensuring CD uniformity) and overlay control prior to lithography.