Via to metal line end process margin calibration by voltage contrast-based EPE process margin

E-beam SEM images cannot fully capture patterning 3D geometry to accurately qualify the impact of unmeasured wafer processing and metrology biases to ensure yield. In this study, we use voltage contrast (VC) as yield proxy to calibrate inline process margin for optimized early yield loss detection and feedback control. The sub nanometer precision of Voltage Contrast based Edge Placement Error gives excellent dual layer SEM contours to VC correlation with <0.3% yield RMSE. This technique is also able to decouple overlay, CD and metrology contributions to correlation variation band.