Photolithography-Induced Doping and Interface Modulation for High-Performance Monolayer WSe₂ P-Type Transistors

To mitigate Fermi-level pinning (FLP) at the contact of two-dimensional (2D) transition metal dichalcogenides and enhance their hole carrier concentration, a 1.8 nm-thick p-doping layer is formed via photolithography. This surface treatment significantly reduces the contact resistance (<i>R</i>_C) to ∼4.8 kΩ·um in monolayer (1L) WSe₂ p-type field-effect transistors (p-FETs) and increases hole carrier concentration by 1.4 times, resulting in a field-effect mobility of ∼75 cm/V·s. After subsequent helium ion-beam lithography, the Fermi level can still be modulated from 4.25 to 4.55 eV due to the ultrathin buffer layer. This approach enables high-performance p-FETs with 1L-WSe₂ channels, achieving a maximum on-state current density of 420 μA/μm at a <i>V</i>_D of -1 V and ultralow <i>R</i>_C of ∼0.8 kΩ·um by the combination of the MoO_<i>x</i> encapsulation for additional p-doping. These results demonstrate that 1L-WSe₂ p-FETs can attain performance comparable to 2D n-FETs, paving the way for high-performance complementary metal-oxide semiconductor transistors with 2D channels.