A 0.16 pJ/bit 32 Gb/s NRZ Equalizer with Fixed Peak Frequency and Tunable Gain in 65 nm CMOS

This research work presents a 32[Formula: see text]Gb/s nonreturn-to-zero (NRZ) equalizer based on the Taiwan Semiconductor Manufacturing Company (TSMC) 65 nm Complementary Metal Oxide Semiconductor (CMOS) process. The system consists of a couple of 50 [Formula: see text] termination, a continuous time linear equalizer (CTLE), a variable gain amplifier and a one-tap decision feedback equalizer. By properly adjusting the [Formula: see text] in the first-stage CTLE, a fixed peaking frequency with a 7 dB compensation is successfully achieved for the proposed analog front end (AFE). Besides, a 16[Formula: see text]GHz bandwidth and a 13[Formula: see text]dB gain tuning range are achieved by adjusting the source degeneration resistors in the AFE. The results indicate that the system compensates a total of 24.7[Formula: see text]dB channel loss at Nyquist frequency and opens the closed eye in the 32[Formula: see text]Gb/s NRZ transmission, hence achieving an eye-opening of 0.83 UI horizontally and 530[Formula: see text]mV vertically. Finally, the complete post-simulation layout area is only 0.0014[Formula: see text]mm 2 . Furthermore, operating with a power consumption of 5.2[Formula: see text]mW, the equalizer exhibits an exceptional energy efficiency of 0.16[Formula: see text]pJ/bit.